November 1st, 2010: IESA-NCR Distinguished Speaker Series  

Story of HDLs : My Perspective

Jayaram Bhasker

eSilicon Corporation

 

The Indian Semiconductor Association’s NCR Chapter is pleased to announce the next talk as part of the IESA-NCR Distinguished Speaker Series by Jayaram Bhasker, Architect, eSilicon Corporation on Monday, 1st November, 2010. Please mark your calendars.

 

Speaker Profile:

Bhasker is a distinguished author and expert in the area of hardware description languages and RTL synthesis. He has published a number of papers in journals and conferences, and has authored numerous books on VHDL, Verilog, SystemVerilog, SystemC and more recently on static timing analysis. Bhasker has served on several conference committees including the Design Automation Conference, Design & Verification Conference (DVCon) and VHDL International Users Forum (VIUF). He has been the chair of two working groups: the IEEE 1076.6 VHDL Synthesis Working Group and the IEEE 1364.1 Verilog Synthesis Working Group and a major contributor to the IEEE Std 1076.3 NUMERIC packages.

Bhasker is currently an Architect at eSilicon Corporation in Allentown, PA, where he guides physical design methodology for all chips that tapeout at eSilicon. He has also been a Senior Architect at Cadence Design Systems, and a Distinguished Member of the Technical Staff at Bell Laboratories. He is the recipient of the Honeywell Excel Pioneer Award (1987) and the IEEE Computer Society Outstanding Contribution Award (2005). Bhasker holds a Ph.D. degree in Computer Science from the University of Minnesota.

When:             Monday, 1st November, 2010

                        Registration:  3:00 – 3:30 pm
                        Talk: 3:30 – 4:45 pm
                        Refreshments and networking: 4:45 – 5:30 pm

 

Venue:            Cadence Design Systems

                        Plot 57 A&B, Noida Special Economic Zone

                        Noida, UP 201305

                        Tel : +91 120 3984000

 

Who should attend: This talk is for senior design engineers, design managers, EDA professionals, graduate level students and faculty of engineering institutes.